The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 17, 2002

Filed:

Feb. 10, 2000
Applicant:
Inventors:

Kenji Sekine, Hinode, JP;

Hiroji Yamada, Shiroyama, JP;

Matsuo Yamasaki, Satsuma, JP;

Osamu Kagaya, Tokyo, JP;

Kiichi Yamashita, Shiroyama, JP;

Assignee:

Hitachi, Ltd., Tokyo, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 2/334 ;
U.S. Cl.
CPC ...
H01L 2/334 ;
Abstract

A metal base substrate for mounting a plurality of bare semiconductor chip devices thereon has first and second main surfaces. The first main surface has formed thereon at least one projection, and at least two recesses in which the bare semiconductor chip devices are to be mounted. The depth of these recesses is smaller than the length of said projection, and the recesses have a higher surface smoothness than said main surfaces of said metal substrate. The metal base substrate is partially chemically etched to form the projection, and the first main surface of the substrate is mechanically worked to form at least the recesses. The conductive projection is isolated from the portion on which the bare semiconductor chip devices are mounted, of the base substrate, and the conductive projection acts as a terminal that can be electrically connected to the outside on the first and second main surfaces of the base substrate.


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