The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 17, 2002

Filed:

Apr. 12, 2001
Applicant:
Inventors:

Donald O. Anstrom, Endicott, NY (US);

Bruce J. Chamberlin, Vestal, NY (US);

John M. Lauffer, Waverly, NY (US);

Voya R. Markovich, Endwell, NY (US);

David L. Thomas, Endicott, NY (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H05K 1/02 ;
U.S. Cl.
CPC ...
H05K 1/02 ;
Abstract

A method and structure for implementing dense wiring, in printed circuit board or chip carrier applications, which provides superior electrical characteristics while preserving the system resistance and characteristic impedance requirements. The dense wiring is characterized by requiring that all wires have a sufficient cross-sectional area to ensure the longest wires used do not exceed a maximum resistance by either sorting wire lengths and allowing acceptably “short” wires to use denser circuit lines or by providing short lengths of short circuit lines in those areas where necessary and switching to less dense, lower resistance lines where possible. The disclosure also provides for dense wiring in component areas that can then be converted to low resistance wiring with application of a buried via.


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