The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 10, 2002
Filed:
Nov. 14, 2000
Masao Hamada, Fukuoka, JP;
Takashi Hashimoto, Fukuoka, JP;
Shun-ichi Kurohmaru, Fukuoka, JP;
Koji Kai, Fukuoka, JP;
Matsushita Electric Industrial Co., Ltd., Osaka, JP;
Abstract
After a program is inputted in the high-level synthesis of system design, blocks each for implementing at least one function and an HW resource connection graph showing a plurality of HW resources and a wiring structure connecting the HW resources are generated. From a database storing the HW resources, data on the size of each of the HW resources is inputted such that the HW resources are provisionally placed and a contribution rate of each of parameters which affect power consumption and the like in each of wires between blocks with respect to all the wires is calculated as a weight of signal lines between blocks. Block generation is performed repeatedly till the weight of signal lines between blocks in each of the wires between blocks becomes a threshold value or less. If the weight of signal lines between blocks becomes the threshold value or less, an HDL is outputted. By performing block generation in consideration of a reduction in power consumption and the like in the high-level synthesis on the high level design, overall design efficiency is increased.