The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 10, 2002
Filed:
Feb. 16, 2001
Puvvada Venugopal, Bangalore, IN;
Snehamay Sinha, Bangalore, IN;
Sridhar Ramaswamy, Plano, TX (US);
Charvaka Duvvury, Plano, TX (US);
Guru C. Prasad, Bangalore, IN;
C. S. Raghu, Scotch Plains, NJ (US);
Gopalaro Kadamati, Plano, TX (US);
Texas Instruments Incorporated, Dallas, TX (US);
Abstract
For quantitatively identifying sensitivities against electrostatic discharge (ESD) and latch-up in an integrated circuit (IC) design (before the actual IC is fabricated), the disclosed computer system and method combine information from the design netlist, the elements model, a safe operating file, and a list of stress simulations, and apply a simulated, quantified ESD event to the design. The observed sensitivities of the design elements to ESD and latch-up are then quantitatively analyzed, critical stress values are judged, and element failures recorded. Finally, element and location lists of sensitivities and failures are output in a specific format.