Parallel input output combined system for producing error correction code redundancy symbols and error syndromes

Abstract

A parallel input/output combined encoding and syndrome generating system encodes two information symbols per clock cycle, and thereafter, produces two redundancy symbols per clock cycle. For an n-symbol code word with 2k information symbols c , to c , the symbols c , c , c . . . are supplied, in turn, to a first input line while the symbols c , c , c , . . . are supplied, in turn, to a second input line. In a first clock cycle, the symbol c is combined with the contents of the R registers, where R is the number of redundancy symbols, and the contents are multiplied by the respective roots of the generator polynomial. The products then are combined with the paired symbol c and the resulting sums are multiplied also by the roots of the generator polynomial. These products are then summed in a chain of R adders and the respective registers are appropriately updated with the results of the encoding of the two symbols. During the next clock cycle, the next pair of information symbols are encoded, with c supplied to the first input line and c supplied to the second input line, and so forth. During the k clock cycle, when the last of the pairs of information symbols are being encoded, the system produces the first two redundancy symbols. The first redundancy symbol is the update value for the last register r , and the system then manipulates the update value, to produce the second redundancy symbol in the same clock cycle. The pair of redundancy symbols are next fed back to the two input lines and encoded, as discussed above. For decoding, the chain of R feedback adders is broken, and each set of adders and multipliers operates separately to update the associated register with the results of the manipulation of two code word symbols per clock cycle.