The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 10, 2002
Filed:
Aug. 12, 1999
David A. Courtright, Los Gatos, CA (US);
Vidya Rajagopalan, San Carlos, CA (US);
Radhika Thekkath, Palo Alto, CA (US);
G. Michael Uhler, Redwood City, CA (US);
MIPS Technologies, Inc., Mountain View, CA (US);
Abstract
An on-chip split transaction system bus having separate address and data portions is provided. The system bus contains separate address and data buses for initiating and tracking out-of-order transactions on either or both of the address or data portions of the bus. The system bus provides communication via a bus interface that includes split transaction tracking and control to establish transaction ID's for each transaction initiated by the bus interface, and to determine whether data appearing on the data portion of the system bus is associated with one of its pending transactions. The bus interface also contains flow control logic to determine whether devices that are to be read from, or written to, by the bus interface, have resources (buffers) available to respond to the transactions. If the resources are available, the flow control logic allows the transactions to proceed, and adjusts its counters to reflect the use of the resources. If the resources are not available, the flow control logic causes the transactions to wait until the resources become available.