The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 10, 2002
Filed:
Mar. 30, 2001
Applicant:
Inventor:
Timothy E. Fiscus, South Burlington, VT (US);
Assignee:
International Business Machines Corporation, Armonk, NY (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03L 7/08 ;
U.S. Cl.
CPC ...
H03L 7/08 ;
Abstract
A delay locked loop circuit for conserving power on a semiconductor chip is provided. The circuit includes a delay chain circuit responsive to a clock input signal for generating an output clock signal having a selectively adjustable delay at an output circuit; a feedback loop circuit connects to and controls said delay chain circuit; and a pre-divider circuit connected to said delay chain circuit, wherein said pre-divider circuit is configured to disable the delay chain circuit when the output clock signal is inactive and the memory device is in an idle state (i.e., all banks closed).