The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 10, 2002

Filed:

Oct. 12, 2000
Applicant:
Inventors:

Laszlo Goetz, Freising, DE;

Stefan Reithmaier, Freising, DE;

Martin Rommel, Freising, DE;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03B 1/00 ;
U.S. Cl.
CPC ...
H03B 1/00 ;
Abstract

A digital driver circuit with one or more CMOS inverters intended as input stages, whereby for the MOS FETs of the inverters the channel width/length (W/L) ratio increases from stage to stage. The digital driver circuit includes an intermediate stage with two further CMOS inverters, connected between a supply voltage Vcc and ground. The driver circuit also includes an output stage having two MOS FETs with the drain terminals of both the MOS FETs of the output stage connected both to each other and to the output of the circuit, the W/L ratio of both MOS FETs exceeding that of the MOS FETs of the intermediate stage. The switch-over of the two MOS FETs of the output stage, occurring with changes of the digital input signal at the input of the circuit, is offset in time with respect to each other, thereby reducing current peaks.


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