The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 10, 2002
Filed:
Apr. 11, 2001
Justin Allan Coppin, Fort Collins, CO (US);
Jonathan P Lotz, Ft Collins, CO (US);
Hewlett-Packard Company, Palo Alto, CA (US);
Abstract
In one embodiment, a circuit is provided that includes a precharge device, a DNG FET transistor, and at least one pull-down FET transistor with a floating body. The precharge device is connected to a precharge node for charging it during a precharge state. The DNG FET transistor is connected between a DNG node and a charge sink for operably linking the DNG node to the charge sink during an evaluate state. In addition, the DNG transistor has an associated precharge leakage current. The at least one pull-down FET transistor has an input threshold voltage whose value is inversely affected by its floating body voltage. The at least one pull-down transistor is connected between the precharge node and the DNG node for discharging the precharge node during the evaluate state if so dictated by logical function input values applied to the pull-down transistors during the evaluate state. The DNG leakage current, during the precharge state, draws a sufficient amount of charge from the DNG node to maintain the at least one pull-down transistor body voltage(s) at a sufficiently low value so that the precharge node does not wrongfully evaluate to a discharge level during the evaluate state.