The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 10, 2002

Filed:

Feb. 12, 2001
Applicant:
Inventors:

Alexander Kalnitsky, Portland, OR (US);

Sang Hoon Park, Portland, OR (US);

Robert F. Scheer, Portland, OR (US);

Assignee:

Maxim Integrated Products, Inc., Sunnyvale, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 2/1331 ;
U.S. Cl.
CPC ...
H01L 2/1331 ;
Abstract

A method of forming an NPN semiconductor device includes the steps of forming a collector region within a substrate, forming a base region over the collector region, and forming an oxide-nitride-oxide stack over the base region. Once these three structures are formed, an opening is created through the oxide-nitride-oxide stack to expose the top surface of the base region. Then, a doped polysilicon material is used to fill the opening and make electrical contact to the base region. The use of the oxide-nitride-oxide stack with appropriate etching of the opening eliminates the exposure of the base region to reactive ion etch environment typical of prior art methods for forming NPN semiconductor devices. As an option, after the opening of the oxide-nitride-oxide stack is formed, a local oxidation of silicon (LOCOS) and etched can be preformed to create oxide spacers to line the opening wall above the base region.


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