The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 10, 2002
Filed:
Oct. 06, 2000
Akira Mineji, Tokyo, JP;
NEC Corporation, Tokyo, JP;
Abstract
A manufacturing method of a semiconductor device, in which a native oxide film on a silicon substrate is removed before ion implantation is performed, and a process that the surface of the silicon substrate is liable to be oxidized, such as a resist removing process, is not to be performed after the ion implantation, is provided. At a source/drain extension region forming process after a gate electrode is formed, a pMOS region is covered with a resist, and As or P is implanted to an nMOS region by low energy implantation. After removing the resist from the pMOS region, a cover insulation film with about 20 nm thickness is disposed on the whole surface of a silicon substrate. The cover insulation film only at the pMOS region is removed by etching back, and a thin film side wall is formed on the gate electrode of the pMOS region. By removing the resist at the nMOS region, a hard mask is formed at the nMOS region, this hard mask works as a mask at the nMOS region when pMOS extension is performed.