The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 03, 2002
Filed:
Apr. 04, 2000
Applicant:
Inventors:
Shinichi Kimura, Osaka, JP;
Hiroyuki Tsujikawa, Shiga, JP;
Assignee:
Matsushita Electric Industrial Co., Ltd., Osaka, JP;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/750 ;
U.S. Cl.
CPC ...
G06F 1/750 ;
Abstract
With respect to layout data of a semiconductor integrated circuit, a latch-up verifying operation is carried out in high precision. In a latch-up verifying method, a well region, a transistor region, and a substrate contact region are extracted from layout data of a semiconductor integrated circuit formed on a semiconductor substrate; and steps for separately setting over-sizing values are sequentially executed based upon the respective extracted information.
Kimura, Shinichi. (2002). Latch-up verifying method and latch-up verifying apparatus capable of varying over-sized region (U.S. Patent No. 6490709). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6490709
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile