Limiting write data fracturing in pci bus systems

Abstract

A system for limiting fracturing of write data by a PCI bus adapter which queues operation commands in a command queue. The write data is in the form of bursts comprising a plurality of contiguous words. Fracture detection logic senses fracturing of the write data. A bus arbiter is responsive to the sensed fracturing of write data by the target, and blocks access to the PCI bus. Queue level detection logic is employed, subsequent to the blocking, to monitor completion of the queued operation commands of the PCI bus target. The bus arbiter is then responsive to the queue level detection logic indicating that the PCI bus target has completed enough operations that a predetermined number (such as one) of the operation commands remain queued at its command queue, and grants access to the PCI bus to complete the burst write operation without fracturing.