The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 03, 2002

Filed:

Aug. 07, 2001
Applicant:
Inventor:

Satoshi Yoshimura, Osaka, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 1/606 ;
U.S. Cl.
CPC ...
G11C 1/606 ;
Abstract

In the test of semiconductor non-volatile memories having floating gates, a plurality of memory cells that are connected to an identical word line are programmed simultaneously. A voltage to complete programming these memory cells is the final voltage. After erasing all of the memory cells, a disturbance stress pulse train having voltages changing in increments are applied up to or before the final voltage. Almost simultaneously, the semiconductor non-volatile memory is tested by measuring the lowest threshold voltage among the memory cells on each word line.


Find Patent Forward Citations

Yoshimura, Satoshi. (2002). Test methods for semiconductor non-volatile memories (U.S. Patent No. 6490198). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6490198

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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