The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 03, 2002

Filed:

Sep. 26, 2001
Applicant:
Inventors:

Choong Kit Wong, Penang, MY;

Sammy Cheung, Pleasanton, CA (US);

Boon Jin Ang, Penang, MY;

Assignee:

Altera Corporation, San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 2/100 ;
U.S. Cl.
CPC ...
H03K 2/100 ;
Abstract

A clock divider is described. The clock divider includes: a positive edge triggered state machine having a first input for receiving a first input signal and a first output for providing a first output signal; a negative edge triggered state machine having a second input for receiving a second input signal and a second output for providing a second output signal; and a first combination logic coupled to the positive edge triggered state machine and the negative edge triggered state machine, the first combination logic having a third input for receiving third input signals and a third output for providing a third output signal, where (1) at least one of the first input signal and the second input signal includes an input clock signal having an input clock signal period, (2) the third input signals include the first output signal and the second output signal, and (3) the third output includes an output clock signal having an output clock signal period, where the output clock signal period is a multiple of the input clock signal period.


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