The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 03, 2002
Filed:
Mar. 08, 2001
Applicant:
Inventor:
Julian L. Jenkins, Santa Cruz, CA (US);
Assignee:
Hiband Semiconductor, Inc., Scotts Valley, CA (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K 1/9094 ;
U.S. Cl.
CPC ...
H03K 1/9094 ;
Abstract
A multilevel logic gate for processing digital data in a semiconductor application is provided. The multilevel logic gate comprises, two or more signal input leads for receiving signal input, two or more signal output leads for outputting signal results and a symmetrical structure of an even number of transistor circuit pairs for combining and amplifying the input signals, the symmetrical structure directly interfacing the input leads. The symmetrical structure causes any input signal to propagate through the structure to output at a same latency as any other input signal to the structure.