The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 03, 2002
Filed:
Jun. 11, 2001
Acer Display Technology, Hsinchu, TW;
Abstract
An electrode bonding structure is disclosed for reducing the thermal expansion of a circuit board during the bonding process of the circuit board and a substrate of a flat display. The electrode bonding structure includes a substrate, a circuit board, and an anisotropic conductive film ACF. A substrate dielectric layer and an indenting pad are formed on the surface of the substrate, and the inner surface of the indenting pad is lower than the surface of the substrate dielectric layer by an indenting depth H . The circuit board is placed parallel to the substrate, and a circuit dielectric layer and a bump pad are formed on the surface of the circuit board. The bump pad is higher than the surface of the circuit dielectric layer by a height H . The ACF is placed between the substrate and the circuit board, and the thickness of the ACF is a thickness H . The position of the indenting pad is corresponded to that of the bump pad, and the height H is not less than the sum of the thickness H and the depth H , that is, H >=H +H . The thermal expansion of the circuit board can be reduced during the bonding process of the substrate and the circuit board and the quality of the display can also be improved.