The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 03, 2002
Filed:
Jul. 03, 2001
Applicant:
Inventors:
Alexander Kalnitsky, Portland, OR (US);
Robert F. Scheer, Portland, OR (US);
Assignee:
Maxim Integrated Products, Inc., Sunnyvale, CA (US);
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 2/176 ;
U.S. Cl.
CPC ...
H01L 2/176 ;
Abstract
A method for manufacturing an integrated circuit structure is disclosed. The method includes providing a layer of porous silicon, and epitaxially growing a high resistivity layer on the layer of porous silicon. Devices are then formed on the high resistivity layer to produce the integrated circuit structure. The integrated circuit structure is attached to a silica substrate, such that the silica substrate is coupled to the devices. Further, surface contacts are provided on the structure. The layer of porous silicon is then removed.