Digital timing recovery using baud rate sampling

Abstract

A baud rate digital timing recovery circuit for use in the read channel of a storage device controller is able to operate nominally at the baud rate by recognizing and compensating for oversampling and undersampling conditions. The read channel includes a sample rate converter for interpolating between digitally sampled values and a digital timing recovery loop that detects a phase error in the interpolated signal and adjusts the interpolation interval accordingly. An accumulator circuit generates a modulo-TS interpolation interval value, where TS is the sampling period. Detection circuitry detects when the interpolation interval value has wrapped through its maximum value or minimum value and generates an oversampling or undersampling signal in response. The oversampling and underampling signals are received by an elastic buffer. The elastic buffer operates to store extra values that are generated during undersampling conditions and also disregards bogus samples that are generated during oversampling conditions, in response to the undersampling and oversampling signals. A mini-elastic buffer, also responsive to the oversampling and undersampling signals may be employed in the phase detection loop. The system can operate at the nominal baud rate or can operate at a half baud rate with two parallel paths for processing two incoming samples with each clock cycle.