The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 26, 2002

Filed:

Nov. 19, 1998
Applicant:
Inventor:

Erwin Lehmann, Berlin, DE;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H04L 1/256 ;
U.S. Cl.
CPC ...
H04L 1/256 ;
Abstract

Described are a measuring method and a measuring tool for data communications networks which make use of asynchronous transfer mode (ATM). At the receiving-side 19.44 Mbit/s parallel port of ATM transmission devices, ATM cells are present, which are composed, for example, of 53 eight-bit width data words, whose 47 useful signal words (payload) originate from originally synchronous digital data strings, whose frequency is determined by the bit rate of the originally synchronous digital data strings, and which permit the cell-by-cell reading out of the payload data, which are fed consecutively and at a higher rate as burst data to a data test receiver, which can ascertain the correct or corrupted receipt of the transmitting-side data, without the need for a timing recovery circuit on the receiving side, so that the measurements can be performed using a constant bit rate and a variable bit rate of the originally synchronous digital data strings. The ATM measuring tool includes an ATM evaluation circuit ( ), from which 47 payload data words are extracted from the data words of each valid ATM cell and are fed with the aid of a 19.44 Mbit/s clocked write signal to the data inputs (d through d ) of a memory ( ), and includes a clocked burst data generator ( ), which in this case uses one eighth of the 19.44 Mbit/s clock pulse to control the reading out of the memory ( ) and the parallel loading of the payload data words into a parallel-to-serial converter ( ) and, moreover, emits a 19.44 Mbit/s burst clock pulse at the output ( ). The converted serial data are supplied as clocked data to a burst-data output ( ). Each data burst and the associated clock-pulse burst are emitted externally to outputs ( or ) and fed as a received signal to a data measuring receiver.


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