Integrated circuit memory devices having multiple input/output buses and precharge circuitry for precharging the input/output buses between write operations

Abstract

Integrated circuit memory devices include precharge controller circuit, which generates a precharge control signal in response to completion of a write operation on a first input/output bus. A precharge circuit drives the first and a input/output buses to a predetermined voltage level in response to the precharge control signal. Multiple switches may be used to couple the first and second input/output buses to the memory cell array and these switches may also be coupled to a column select line. The switches may be responsive to a column select signal carried on the column select line such that one or more memory cells are coupled to the first input/output bus and one or more memory cells are coupled to the second input/output bus simultaneously. Because both of the input/output buses are coupled to the memory cell array in response to the column select signal, the memory cell array may be susceptible to bit line disturbance in which charges remaining on one input/output bus from a previous write operation corrupt memory cells during a write operation on a second input/output bus. By driving the first and second input/output buses to a predetermined voltage level after completing a write operation on one of the two input/output buses, bit line disturbance may be prevented.