Vertical fuse structure for integrated circuits containing an exposure window in the layer over the fuse structure to facilitate programming thereafter

Abstract

According to the present invention, after manufacture of a disconnect fuse circuit, windows are opened in the insulating film overlying the second interconnect layer at all possible disconnection points, the disconnection points preferably being an exposure window that is aligned over a disconnect fuse circuit that includes a via that electrically connects electrical conductors disposed on different respective layers. This insulating film may consist of one or more layers of one or more materials, but preferentially consists of a single layer of silicon oxide. The wafer is then stored for later configuration. When the wafer is to be configured, a non-precision mask is manufactured. The wafer is coated with photoresist and patterned using the mask to produce disconnection holes in the photoresist at the desired disconnection points. Since the area over the desired disconnection points are free of the insulating film overlying the second patterned interconnect layer, the etching process can be limited to etch techniques which are optimized to etch metal with selectivity to the insulating film. The areas at the disconnection sites that are covered by the insulating film are further protected during the etch process, since the insulating film acts as an etch barrier to inhibit the etching of active circuit elements in proximity to the desired disconnect points.