The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 26, 2002
Filed:
Mar. 09, 2000
Yumiko Ohshima, Yokohama, JP;
Naoko Yamaguchi, Yokohama, JP;
Kabushiki Kaisha Toshiba, Kawasaki, JP;
Abstract
According to a fabricating method of the present invention, a cap shaped cover plate having a concaved portion on the inner surface is mounted on the rear surface of a semiconductor chip. After solder bumps are formed on a connecting pad of a wiring substrate, a fluid resin layer is formed on the bump formed surface. Thereafter, the semiconductor chip with the cover plate adhered is mounted with a face down on the resin layer formed surface of the wiring substrate. The solder bumps on the chip side and the solder bumps on the substrate side are contacted. At that time, the peripheral portion of the cover plate is contacted and adhered to the wiring substrate. Thereafter, while the bumps on the chip side and the bumps on the substrate side are being heated, melted, and connected, the fluid resin layer on the wiring substrate is hardened. Thus, the space between the semiconductor chip and the wiring substrate (namely, the height of the bumps) is controlled to a predetermined value. As a result, a semiconductor device having a flip-chip bonded portion with high reliability can be fabricated with simplified steps and high yield.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile