The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 19, 2002

Filed:

Aug. 15, 2000
Applicant:
Inventors:

John G McBride, Ft Collins, CO (US);

Jan Kok, Fort Collins, CO (US);

Assignee:

Hewlett-Packard Company, Palo Alto, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 1/750 ;
U.S. Cl.
CPC ...
G06F 1/750 ;
Abstract

An electrical rules checker system and method are provided to appraise tri-state logic connected to a selected node of an integrated circuit by evaluating a netlist. In accordance with one aspect of the invention, the method selects a circuit configuration to be identified. Next, the method identifies any of the circuit configurations at the node, and identifies any probable circuit configurations at the node. Then the method appraises the circuit configurations and the probable circuit configurations. In accordance with another aspect of the invention, a system is provided for appraising tri-state logic connected to a selected node of an integrated circuit. The system operates by evaluating a netlist at the node, and further includes a code segment for selecting a circuit configuration to be identified, a second code segment for identify any of the selected circuit configurations a given node in a netlist, and a third code segment configured to identify any probable circuit configurations at the node in a netlist. A fourth code segment appraises the identified circuit configurations and probable circuit configurations.


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