The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 19, 2002
Filed:
Feb. 07, 2000
Applicant:
Inventors:
Gitu Jain, San Jose, CA (US);
Soren T. Soe, San Jose, CA (US);
Assignee:
Xilinx, Inc., San Jose, CA (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 1/750 ;
U.S. Cl.
CPC ...
G06F 1/750 ;
Abstract
A method and apparatus for implementing incremental design changes. In various embodiments, primary outputs of a new design are compared for logical equivalence to corresponding primary outputs of a prior implementation. If the logic is equivalent, the implementation of the primary outputs from the prior implementation is reused to implement the corresponding primary outputs of the new design.
Jain, Gitu. (2002). Incremental logic synthesis system for revisions of logic circuit designs (U.S. Patent No. 6484292). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6484292
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile