The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 19, 2002

Filed:

Mar. 16, 2001
Applicant:
Inventors:

Mutsumi Hosoya, Fujimi, JP;

Michitaka Yamamoto, Machida, JP;

Assignee:

Hitachi, Ltd., Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/202 ;
U.S. Cl.
CPC ...
G06F 1/202 ;
Abstract

A cache access control system for dynamically conducting specification of dedicated and common regions and thereby always conducting optimum cache coherency control. In a processor, an L cache including an L data array and a directory is provided. A plurality of L caches are connected to each L cache. The L caches are connected to a main memory L . An L cache history manager is supplied with L cache status information and an L cache access request from L caches. The L cache history manager judges an attribute (a dedicated region or a common region) of each line of L . On the basis of the attribute, a cache coherency manager conducts coherency control of each L cache by using an invalidation type protocol or an update type protocol. The attribute is judged to be the common region, only in the case where a line shared by a plurality of L caches in the past is canceled once by the invalidation type protocol and then accessed again.


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