The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 19, 2002

Filed:

Apr. 13, 2001
Applicant:
Inventor:

Young-Gu Kang, Kyunggi-do, KR;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 7/00 ;
U.S. Cl.
CPC ...
G11C 7/00 ;
Abstract

A semiconductor integrated circuit includes a memory cell array, a read circuit that reads test data from the memory cell array, a parallel test control circuit, a bit organization address control circuit, and a parallel test circuit. The parallel test control circuit, in response to a wafer test flag signal, a package test flag signal, and a bank activation signal, generates a first control signal and a second control signal. The bit organization address control circuit, in response to the wafer test flag signal, the package test flag signal, the bank activation signal, and a bit organization information signal, generates a third control signal. The parallel test circuit, in response to the first and second control signals, determines whether all bits of the test data read have the same logic levels. The first, second, and third control signals determines where the test data are read from in the memory cell array.


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