The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 19, 2002

Filed:

Sep. 01, 1999
Applicant:
Inventors:

Jae-Hee Kim, Kyungki-do, KR;

Young-Man Ahn, Kyungki-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/00 ;
U.S. Cl.
CPC ...
G11C 7/00 ;
Abstract

Integrated circuit test systems include an input driver having an output terminal that is connected to a test system port and a biasing device that is connected between the test system port and a reference voltage. The biasing device comprises a Thévenin equivalent circuit that is represented by an impedance element and a nonzero power source. The impedance element may be used to match the impedance of a device under test, which can reduce distortion in signals passed between the device under test and the test system. Furthermore, the power source may be used to provide direct current (DC) signals at the pins of a device under test, which can allow the swing height (e.g., amplitude or magnitude) of the test signals to be reduced. That is, the test signals are superimposed upon the DC voltages to allow “high” and “low” logic levels to be manifested via relatively minor swings in the test signals. By reducing the swing height of the test signals, transmission speed can be improved thereby reducing round trip signal delay.


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