Digital display unit which adjusts the sampling phase dynamically for accurate recovery of pixel data encoded in an analog display signal

Abstract

A digital display unit adjusting the phase of a sampling clock based on the examination of a display data signal contained in a received analog display signal. The phase may be adjusted by determining a boundary between display data portions representing successive pixel data elements. As the boundaries provide the timing information related to the source clock, the phase of the sampling clock can be adjusted when ever the boundaries can be determined accurately. The phase of the sampling clock can be adjusted potentially every sampling clock cycle if the boundaries can be determined. The area for examination can be minimized by first determining an expected boundary based on synchronization signal accompanying the analog display data, and examining only a small area surrounding the expected boundary.