The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 19, 2002

Filed:

Apr. 10, 2000
Applicant:
Inventors:

Soo-Cheol Lee, Seoul, KR;

Jong-Hyon Ahn, Kyonggi-do, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 2/166 ;
U.S. Cl.
CPC ...
H01L 2/166 ;
Abstract

A method of fabricating a semiconductor device is provided that includes forming first and second gate electrodes on a substrate via a first photo mask, in which the first and second gate electrodes are in a longitudinal direction parallel to respective channels arranged in x-axis y-axis directions, measuring and comparing the lengths of the first and second gate electrodes on the substrate, estimating a mask bias on the basis of the difference between the actually measured lengths of the gate electrodes, and forming patterns of the first and second gate electrodes of which lengths are adjusted with the estimated mask bias on a new second photo mask, so that the first and second gate electrodes of the same length are formed on the same substrate via the new, second photo mask, regardless of the arrangement directions of the gate electrodes in parallel to channels. This has the effect of improving the processing speed of high CPU or logic element and the yield of products manufactured by this process.


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