The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 12, 2002
Filed:
Feb. 16, 2001
Susumu Watanabe, Kanagawa-Ken, JP;
Kabushiki Kaisha Toshiba, , JP;
Abstract
An LSI mask writing data compressing system and method according to the present invention generates first-coordinate-axial one-dimensional arrays for each individual layout pattern, each of which comprises individual layout patterns having the same shape repeatedly arranged at regular intervals in the direction of a first coordinate axis, second-coordinate-axial one-dimensional arrays for each individual layout pattern, each of which comprises individual layout patterns having the same shape repeatedly arranged at regular intervals in the direction of a second coordinate axis perpendicular to the first coordinate axis, two-dimensional arrays for each individual layout pattern, each of which comprises first-coordinate-axial one-dimensional arrays for each individual layout pattern repeatedly arranged at regular intervals in the direction of the second coordinate direction, a first-coordinate-axial block array of multiple layout patterns, which comprises grouped first-coordinate-axial one-dimensional arrays for each individual layout pattern, which include the same number of individual layout patterns repeatedly arranged at the same regular intervals in the direction of the first coordinate axis, a second-coordinate-axial block array of multiple layout patterns, which comprises grouped second-coordinate-axial one-dimensional arrays for each individual layout pattern, which include the same number of individual layout patterns repeatedly arranged at the same regular intervals in the direction of the second coordinate axis, and a two-dimensional block array of multiple layout patterns, which comprises grouped two-dimensional arrays of individual layout patterns, which include the same number of individual layout patterns repeatedly arranged at the same regular intervals, to convert data for each of the arrays to prepare writing data for a hierarchical cell.