Method and system for proactively debugging fitting problems in programmable logic devices

Abstract

A method and system for automatically proactively debugging fitting problems in programmable devices. Automatic fitters are computer programs that place and route circuit resources within a programmable device, e.g., a complex programmable logic device (CPLD) to determine the resources used and timing for a given hardware design. Upon a fitting failure for an IC or hardware design, an embodiment first may identify any specific architectural information, if any, causing the failure and may advise the user including solution recommendations. Second, an embodiment obtains a larger device having the same pin package, if available, or a virtual device, and may perform a second fitting on the hardware design but using this larger device. If this fits properly, then the resulting pin assignment is fixed and a third fitting may be performed on the smaller device with the fixed pin assignment. If this fails, further architectural violations are identified and solution recommendations are given to the user. If there are no larger devices that can be used with the hardware design and/or the third fitting does not obtain a proper result, then an embodiment determines if specific named pins are failing to fit. If these pins are identified, and the user has not locked them down, then they may be allowed to float and fitting is performed once more. If no solution can be reached after the above attempts, then an embodiment informs the user that technical support is required and a history of the fitting attempts may be recorded. A programming file may be generated on a successful fit.