The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 12, 2002

Filed:

Apr. 29, 2000
Applicant:
Inventors:

Robert C. Douglas, Santa Clara, CA (US);

Kent A. Dickey, Westford, MA (US);

Assignee:

Hewlett-Packard Company, Palo Alto, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 1/200 ;
U.S. Cl.
CPC ...
G06F 1/200 ;
Abstract

A method provides for interleaved access of a contiguous logical address space formed by a plurality of memories having respective overlapping address spaces. The memories are organized into memory segments, memory segments of equal size from different memories arranged or organized into interleave groups. An initial largest interleave group is selected and a corresponding first interleave entry is generated in a table. The interleave entry maps a corresponding initial logical address space into each of the memory segments corresponding to the first interleave group. A total memory size included thus far in the table is calculated and successive next larger groups that are integer divisors of the total memory, i.e., the partial sums formed by groups selected thus far. These steps are repeated until all of the contiguous logical address space has been mapped onto the memories. A mask may be used to extract portions from a logical address to index into a table mapping the logical address space onto the memories. Another portion of the logical address includes a memory offset.


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