The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 12, 2002
Filed:
Sep. 01, 1994
Michael J. Peters, Fort Collins, CO (US);
Richard L. Collins, Fort Collins, CO (US);
David M. Musolf, Fort Collins, CO (US);
Patrick R. Bashford, Fort Collins, CO (US);
Bradley J. Wright, Fort Collins, CO (US);
Hynix Semiconductor, Inc., Seoul, KR;
Abstract
A design system for modeling bi-directional pad cells, the interaction of internal pull cells/resistors with pad cells of all types, and the interaction of external pull cells/resistors with pad cells of all types. This modeling technique involves the use of three separate pins on each bi-directional pad cell: an input-only pin, an output-only pin, and a resolved pin. The input-only pin reflects the data that is supplied to the pad from external sources. The output-only pin reflects the data that is supplied as output from the pad cell (strong data from the output driver). The resolved pin reflects the combination of the input and the output data that are present, as well as the effect of resistive data supplied by pull-up/down resistors/cells. The output-only and resolved pins are implemented as internal or hidden pins within a pad cell model. These pins are included in the model for the I/O pad cells in a given library. The existing pad pin serves as the input-only pin. The model provides two modes of operation such that the same model can be used for either chip-level or system-level simulations.