The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 12, 2002
Filed:
Jun. 04, 2001
Gregory D. Cooper, Greenbelt, MD (US);
Richard M. Mohring, Wheaton, MD (US);
Pixelligent Technologies LLC, Alexandria, VA (US);
Abstract
The present invention overcomes many of the disadvantages of prior lithographic microfabrication processes while providing further improvements that can significantly enhance the ability to make more complicated semiconductor chips at lower cost. A new type of programmable structure for exposing a wafer allows the lithographic pattern to be changed under electronic control. This provides great flexibility, increasing the throughput and decreasing the cost of chip manufacture and providing numerous other advantages. The programmable structure consists of an array of shutters that can be programmed to either transmit light to the wafer (referred to as its “open” state) or not transmit light to the wafer (referred to as its “closed” state). The programmable structure can comprise or include an array of selective amplifiers. Thus, each selective amplifier is programmed to either amplify light (somewhat analogous to the “open” or “transparent” state of a shutter) or be “non-amplifying” (its “closed” or “opaque” state). In the non-amplifying state, some portion of the incident light is transmitted through the amplifier material. The shutters and selective amplifiers can work in tandem to form a “programmable layer”. A programmable technique is provided for creating a pattern to be imaged onto a wafer that can be implemented as a viable production technique. Thus, the present invention also provides a technique of making integrated circuits. A diffraction limiter can be used to provide certain advantages associated with contact lithography without requiring some of the disadvantages of contact lithography.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile