The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 12, 2002

Filed:

Jun. 05, 2000
Applicant:
Inventor:

Kazuhiro Teramoto, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 1/7735 ;
U.S. Cl.
CPC ...
H03K 1/7735 ;
Abstract

A plurality of the P-channel transistors of Group A and a plurality of P-channel transistors of Group B are connected between the power-supply-voltage VCC and the ground, and an output signal SUBUP is obtained from the node C via two inverters. Each terminal of. Transistors of Group B is connected to the ground via N-channel first, second and third transistors. The first signals &phgr;1 and &phgr;2 are inputted to the gates of the first and second transistors and the output of the NOR logical circuit is inputted to the gate of the third transistor. Current performance of the P-channel transistors of Group B is adjusted to control the substrate voltage and to make the substrate voltage both higher and lower than that of normal operation by the use of the test modes. So, the substrate voltage can be changed during hold tests in a selection process to accelerate the tests and shorten the selection time.


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