The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 12, 2002
Filed:
May. 17, 2001
Applicant:
Inventors:
Hazem Abdel-Maguid, Nepean, CA;
Simon J. Skierszkan, Kanata, CA;
Assignee:
Zarlink Semiconductor Inc., Kanata, CA;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03L 7/00 ;
U.S. Cl.
CPC ...
H03L 7/00 ;
Abstract
A digital phase locked loop (PLL) for recovering a stable clock signal from at least one input signal subject to jitter. The PLL has a digital controlled oscillator for generating a desired output and a stable local oscillator or providing clock signals. A plurality of hierarchical, multi-stage delay lines are provided to generate the required output frequencies for stable T1, E1 and ST3/OC3 timing references.