The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 12, 2002

Filed:

Jun. 26, 2001
Applicant:
Inventors:

Mark W. Morgan, Allen, TX (US);

Fernando D. Carvajal, Fairview, TX (US);

Roy C. Jones, III, Dallas, TX (US);

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K 1/902 ; H03K 1/901 ;
U.S. Cl.
CPC ...
H03K 1/902 ; H03K 1/901 ;
Abstract

A low voltage 485-driver circuit that meets the standard leakage and 1.5 voltage differential output requirements of the TIA/EIA-485 specification while operating from a 3V supply. The circuit avoids the voltage drop across the series Schottky diodes in the output driver of a conventional 485-driver by moving the Schottky blocking diodes from the output stage signal path to the pre-driver stage so that the output stage is restricted to back-gate biasing only. In addition, the circuit uses stacked NMOS transistors to maintain lower voltage across each NMOS transistor in order to prevent hot-carrier injection. This allows lower voltage rated output NMOS transistors to be used, resulting in higher speed operation. The circuit will withstand excessive common mode voltages in the range of +12V to −7V applied to the output while in either signaling ON state or the disabled OFF state.


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