Breakpoint interrupt generating apparatus in a superscalar microprocessor

Abstract

The present invention provides a breakpoint interrupt generation apparatus in a superscalar microprocessor, which can be implemented by small amount of hardware resources, thereby reducing required chip area. The breakpoint interrupt generation apparatus in a n-way superscalar microprocessor comprises: an address control element for receiving a plurality of addresses and a plurality of request signals generated for memory access and for producing the received address one-by-one for one cycle; a breakpoint address storage for storing an intended address for breakpoint generation; a control information storage for storing control information required for breakpoint generation; an address match element for comparing the address from said breakpoint address storage with the address applied from the address control element so as to produce a match signal indicating whether the two addresses are identical; and an enable element for checking whether a breakpoint is generated every cycle based on the match signal from the address match element, the control information from the control information storage and a bus cycle information and for generating a breakpoint interrupt signal in response to a complete signal from the address control element.