Branch instruction mechanism for processor

Abstract

An improved branch instruction and associated branch control instruction are provided for optimizing handling of branch operations within a pipelined processor. The branch control instruction is adapted so that it can precede the branch instruction in a program sequence and provides branch target address computation information so that branch target addresses can be computed in advance of execution of one or more associated branch instructions. The branch control instruction also includes its own branch instruction prediction bit for specifying to a prefetcher within the processor whether a common branch instruction is likely to be needed by the processor, as well as a ranking field for specifying a preloading priority for the particular common branch instruction. Because branch target address computation information is disassociated from the actual branch instruction, more space is available within the branch instruction itself to permit additional new types of operations, such as folded-compare, register to register comparisons (including a compare to a zero valued register), predicate evaluations, etc. A separate prediction bit within the branch instruction specifies whether the branch is likely to be taken or not taken to a branch control unit in the processor, and it is these separate prediction bits that are considered by a branch control instruction for a group of branch instructions to determine the branch instruction prediction bit.