Field-configurable, adaptable and programmable input/output bus interface and method

Abstract

A self-configurable, adaptable and programmable (hereinafter “CAP”) I/O bus ( ) is provided in a digital computer ( ) to establish compatibility between the input/output bus of computer ( ) and an incompatible input/output bus of an external module ( ). Computer ( ) includes a field programmable gate array (FPGA) ( ) for translating the bus configuration used by module ( ) to that employed by computer ( ). Two preselected CAP I/O Bus conductors ( ) pass an identification number from the module ( ) to computer ( ) that points to the location of the information necessary to compatibly configure FPGA ( ). This information, which includes a bus logic FPGA image file and a device driver, and may include a protocol driver, may be found in one of several locations, including onboard computer ( ) in memory, onboard module ( ), or at an external site such as a server ( ) accessible via the Internet. Computer ( ) retrieves the configuration information from the location corresponding to the identification number, configures FPGA ( ) and establishes communication between the two input/output buses.