The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 05, 2002
Filed:
Feb. 01, 2002
Applicant:
Inventor:
Goran Bilski, San Jose, CA (US);
Assignee:
Xilinx, Inc., San Jose, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 7/38 ; H03K 1/977 ;
U.S. Cl.
CPC ...
G06F 7/38 ; H03K 1/977 ;
Abstract
Structures and methods that implement an ALU (Arithmetic Logic Unit) circuit in a PLD (Programmable Logic Device) while using only one PLD logic cell to implement a one-bit ALU circuit. The ALU circuit has two data input signals and two operator input signals that select between the adder, subtractor, and other logical functions. A result bit provides the result of the addition, subtraction, or other logical function as selected by the values of the two operator input signals. A carry chain is provided for combining the one-bit ALU circuits to generate multi-bit ALUs. All of this functionality is implemented in a single PLD logic cell per ALU bit.