The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 29, 2002

Filed:

Sep. 28, 1999
Applicant:
Inventors:

Krunali T. Patel, Allen, TX (US);

Mark A. Beadle, Allen, TX (US);

David W. Rekieta, McKinney, TX (US);

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 3/00 ;
U.S. Cl.
CPC ...
G06F 3/00 ;
Abstract

A controller ( ) for coupling between a computer bus ( ) and one or more units ( ) compatible with the bus. The controller comprises a first input ( ) for receiving a first reset signal issued from the computer bus, and a second input ( ) for receiving a second reset signal. The controller further comprises circuitry ( ) for storing a first set of information which will be cleared in response to assertion of the first reset signal. Lastly, the controller comprises circuitry ( ) for storing a second set of information which will not be cleared in response to assertion of the first reset signal but which will be cleared in response to assertion of the second reset signal. In a described embodiment, the bus is a PCI bus, the first reset signal is a PCI Reset signal, and the second reset signal is an initialization signal.


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