Method for compensating a phase delay of a clock signal

Abstract

A method compensates a phase delay of a clock signal used in a data communications system. First, a plurality of delayed clock signals are provided by modifying the amount of delay of the clock signal. In synchronization with one of the delayed clock signals, one or more test data signals and their address signals are sequentially issued and sent to a storage device. In synchronization with the original clock signal, each test data signal is stored in an area that its address signal indicates and then, upon receipt of the address signal at a predetermined time of the original clock signal, a data signal which corresponds to the address signal is read and sent to a controller. At a predetermined time of the delayed clock signal, a data signal is received from the storage device and it is checked whether or not each test data signal and the received data signal are the same. If it is checked to be positive, the process is repeated for a next test data signal and, if otherwise, the process is repeated for a next delayed clock signal until it becomes checked to be positive. Finally, if it is checked to be positive with respect to all the one or more test data signals, the delayed clock signal is decided as a definitive clock signal to be used in the semiconductor device, and if not, the process is repeated for a next delayed clock signal until it becomes checked to be positive.