The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 29, 2002

Filed:

Sep. 17, 1999
Applicant:
Inventors:

Tatsumi Yamauchi, Hitachiohta, JP;

Kazuharu Kuchimachi, Hadano, JP;

Assignee:

Hitachi, Ltd., Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 5/12 ;
U.S. Cl.
CPC ...
H03K 5/12 ;
Abstract

A third gate circuit which is controlled by a clock signal and operates upon the detection of change of a signal on a critical path driven by a first gate circuit and transmits a signal provided by the first gate circuit to a second gate circuit is connected to the critical path at a position near the second gate circuit. The third gate circuits operates upon the detection of change of the signal to increase the speed of change of the signal. Thus, the ratio of a delay time attributable to wiring resistance in the critical path of a semiconductor integrated circuit is reduced, the speed of the critical path is increased and the operating frequency of the semiconductor integrated circuit can be improved.


Find Patent Forward Citations

Yamauchi, Tatsumi. (2002). Semiconductor integrated circuit device having compensation for wiring distance delays (U.S. Patent No. 6472917). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6472917

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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