The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 29, 2002

Filed:

Aug. 04, 1999
Applicant:
Inventors:

Kerry Veenstra, San Jose, CA (US);

Krishna Rangasayee, Sunnyvale, CA (US);

John E. Turner, Santa Cruz, CA (US);

Assignee:

Altera Corporation, San Jose, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K 1/9173 ; H03K 1/9177 ;
U.S. Cl.
CPC ...
H03K 1/9173 ; H03K 1/9177 ;
Abstract

In a programmable logic device, input/output circuits are grouped into blocks. Each block includes input/output circuits capable of handling a plurality of logic signalling schemes, which may require different supply voltages and reference voltages. Each block also has its own power supply bus. In this way, the different blocks can be provided with different supply and reference voltages, so that different blocks can be used for different logic signalling schemes, thereby allowing more than one such scheme to be used simultaneously on a single device. A single block could also be implemented with more than one scheme active, as long as all of the schemes in use in the block have the same power supply requirements and—to the extent that each such scheme requires a reference voltage—the same reference voltage requirements.


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