The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 29, 2002

Filed:

Jun. 06, 2001
Applicant:
Inventors:

Byung Hee Cho, Kyungki-do, KR;

Noh Yeal Kwak, Kyungki-do, KR;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 2/1336 ;
U.S. Cl.
CPC ...
H01L 2/1336 ;
Abstract

A method of manufacturing a flash memory device includes the steps of sequentially forming a tunnel oxide film and a first polysilicon layer on a semiconductor substrate in which a device separation film is formed and then patterning the tunnel oxide film and the first polysilicon layer to form a floating gate; forming a mask so that a portion in which a source region will be formed can be exposed and then removing the device separation film at the exposed portion; forming a dielectric film including a lower oxide film, a nitride film, and an upper oxide film on the entire structure; performing an annealing process; then forming a second polysilicon layer on the dielectric film; sequentially removing the polysilicon layer, the upper oxide film, and the nitride film in a portion in which a source region and a drain region will be formed, and injecting impurity ions into the semiconductor substrate at a portion in which the lower oxide film remains to form a source region and a drain region; after removing the remaining lower oxide film, sequentially forming a third polysilicon layer and a tungsten silicide layer on the entire structure and then patterning the third polysilicon layer and the tungsten silicide layer to form a control gate; and performing an annealing process for activating the impurity ions injected into the source region and the drain region.


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