The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 6472234 B1

PDF
Full Text
Expired
Date of Patent:
Oct. 29, 2002

Filed:

Apr. 02, 2001
Applicant:
Inventor:

Tadashi Ozawa, Tokyo, JP;

Assignee:

NEC Corporation, Tokyo, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G01R 3/126 ; H01L 2/166 ;
U.S. Cl.
CPC ...
G01R 3/126 ; H01L 2/166 ;
Abstract

In a failure analysis method for a ball grid array type semiconductor device including a semiconductor chip having pads, first solder balls, an interposer substrate and second solder balls, the second solder balls and the interposer substrate are removed from the semiconductor device, and then, the first solder balls are removed from the semiconductor device. Then, the semiconductor device is mounted on a package, and a wire bonding operation is performed between the pads of the semiconductor chip and bonding pads of the package. Finally, a test operation is performed upon the semiconductor chip by mounting the package on a tester.


Find Patent Forward Citations

Ozawa, Tadashi. (2002). Failure analysis method for chip of ball grid array type semiconductor device (U.S. Patent No. 6472234). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6472234

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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