The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 22, 2002
Filed:
May. 18, 2000
Brian A. Day, Colorado Springs, CO (US);
Coralyn S. Gauvin, Colorado Springs, CO (US);
LSI Logic Corporation, Milpitas, CA (US);
Abstract
A method for defining electrical components enables a layout tool to include functionally extraneous cells in an integrated circuit design without significant adverse impact to the operation of the logically functional cells. The method defines the description of a first functionally extraneous cell for a layout tool so an initial layout of the die produced by the layout tool does not functionally couple the first functionally extraneous cell to a second functionally extraneous cell. The description of the functionally extraneous cell is altered so that the layout tool produces a second layout of the die that functionally couples the first and second functionally extraneous cells without altering the position of the second functionally extraneous cell with respect to a logically functional cell. The description of the functionally extraneous cell complies with the description constraints for cells. However, by describing the functionally extraneous cell so that it is first lacks a functional coupling to another extraneously functional cell and then changing the description to functionally couple the two cells, the position of the second functional cell with respect to a functional cell remains unchanged. In this manner, the advantages of the layout tool may be used to most efficiently locate the cells of the logically functional cells and then couple test circuitry or other functionally extraneous circuits without adversely impacting the operation of the functional logic in a significant way.