The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 22, 2002
Filed:
Apr. 13, 2000
Shigehisa Yamamoto, Tokyo, JP;
Mitsubishi Denki Kabushiki Kaisha, Tokyo, JP;
Abstract
A method of verifying semiconductor integrated circuit reliability allows reliability verification of a large-scale semiconductor integrated circuit without any omission. Step S is to obtain a sum total (Cio) of inner-cell input/output load capacities in a selected cell on the basis of input and output load capacities registered in a cell library database ( A), and step S is to obtain wiring capacitance (Cic) between cells. In step S , the sum total (Cio) of inner-cell input/output load capacities and the wiring capacitance (Cic) between cells are added to obtain output-terminal load capacity (COUT). On the basis of the output-terminal load capacity (COUT), a failure rate (FOUT) of an intercellular interconnect line is obtained in step S , and a failure rate (Fcell) of inner-cell interconnect lines is obtained in step S from an equation registered in the cell library database ( A). Then, those failure rates (Fcell, FOUT) are added to obtain a total failure rate (Ftotal) in step S